1. Field of the Invention
The present invention relates to the field of fabrication of integrated circuits, and, more particularly, to the cleaning of substrates on which integrated circuits are formed at the manufacture of metallization layers according to the so-called damascene technique.
2. Description of the Related Art
A typical process in the manufacturing of integrated circuits is the formation of conductive vias for wiring, i.e., electrically connecting individual components of the integrated circuit. A widely used process for surface wiring the individual components of an integrated circuit, also referred to as “metallization,” is the so-called damascene process in which trenches are formed in an insulating layer and subsequently filled with a conductive material to form the conductive lines and vias. Currently, most of the silicon-based semiconductor chips comprise a metallization layer including silicon dioxide as a dielectric material and aluminum as the conductive material due to the aluminum's excellent adhesion to the surrounding silicon dioxide without any tendency to diffuse into the silicon dioxide.
In view of the increasing demand for high performance semiconductor chips over the past several years, efforts have been made to improve the electrical conductivity in metal connections electrically connecting the various individual components. In particular, copper has been proven to be a promising candidate for replacing the aluminum due to its lower specific resistivity, which is about one order of magnitude smaller than that of aluminum. Moreover, contrary to aluminum, copper does not show eutectic reactions and thermally-induced electromigration when used in very large scale integration (“VLSI”) and ultra-large scale integration (“ULSI”) semiconductor chips. Additionally, copper is capable of being deposited at low temperatures in openings having high aspect ratios, thereby yielding a good step coverage. The use of electrochemical deposition techniques for copper deposition is especially appealing due to low cost, high throughput, high quality of the deposited copper film, and excellent via/trench filling capabilities.
In order to provide a highly reliable integrated circuit, the metal of the interconnecting lines and vias has to sufficiently adhere to the surrounding dielectric material, and diffusion of the metal atoms into the dielectric material must be reduced as much as possible. Thus, in many cases, the metal may not be directly deposited onto the dielectric material, but a barrier layer has to be deposited on the surface of the dielectric layer prior to the deposition of the metal. For example, copper readily diffuses into silicon dioxide and does not adhere to silicon dioxide very well. Accordingly, a thin barrier layer, for instance comprising tantalum, is deposited to provide sufficient adhesion of the copper and to prevent diffusion of the copper into the silicon dioxide.
A typical prior art metallization process will be described in the following with reference to FIGS. 1a–1c. In FIG. 1a, a schematic cross-sectional view is shown of a semiconductor structure 100 including a substrate 101 having formed thereon a plurality of circuit elements that are for convenience not depicted. A first insulating layer 102 is formed over the substrate 101 and comprises a metal line 104 with a barrier layer 103 disposed between the insulating layer 102 and the metal line 104. The insulating layer 102 may, for example, be comprised of silicon dioxide, silicon nitride and the like. The metal line 104 may be a copper line and the barrier layer may comprise tantalum, tantalum nitride and the like. A second insulating layer 105 comprised of, for instance, silicon dioxide or silicon nitride, and a resist layer 106 are formed over the substrate 101, wherein an opening, in the present example a via 109, is formed in the insulating layer 105 and the resist layer 106. The semiconductor structure 100 is meant to represent a damascene structure in which an electrical connection is to be established between a first metallization layer, defined by the insulating layer 102 and the metal line 104, and a second metallization layer to be formed over the insulating layer 105, wherein the via 109 that is to be filled with copper provides this electrical connection.
A typical process flow for forming the semiconductor structure 100 may include the following steps. After formation of the first metallization layer, i.e., the insulating layer 102 and the metal line 104, the substrate 101 is planarized by chemical mechanical polishing and insulating material is deposited by any appropriate deposition method, such as chemical vapor deposition, to form the insulating layer 105. For the sake of simplicity, the deposition of any anti-reflective coating that may be necessary for further processing is not depicted. Subsequently, the photoresist layer 106 is coated on the insulating layer 105 and is patterned according to well known photolithography and etch techniques to form an opening 107 in the resist layer 106. Next, an anisotropic etch step, as indicated by arrows 108, is carried out to form the via 109 above the metal line 104.
FIG. 1b shows the semiconductor structure 100 with the resist layer 106 removed and with a barrier layer 110, for example comprised of tantalum or tantalum nitride, formed in the via 109 and on a surface 112 of the insulating layer 105. A seed layer 111, comprised of copper, is formed on the barrier layer 110.
Typically, after removing the resist layer 106, a cleaning process is preformed to remove any residuals and contaminants within the via 109 and the surface 112, which may otherwise compromise the further process step required for depositing the bulk copper and decrease the quality of the electrical connection to be formed in the via 109. Cleaning the portion of the metal line 104 exposed by the via 109 typically includes a first step, also referred to as out-gassing or degassing, where the semiconductor structure 100 is inserted in a degas chamber. During out-gassing, the temperature of the substrate is raised to promote the removal of contaminants from the surface 112 and the via 109. Subsequently, a so-called pre-clean step is carried out by introducing argon gas into the process chamber and applying a high frequency electric field to establish a plasma ambient for further removal of the contaminants. After cleaning the metal line 104 and the via 109, the barrier layer 110 is deposited by any appropriate deposition method, such as sputter deposition, using an appropriate sputter target and plasma ambient to provide the desired material composition of the barrier layer 110. Subsequently, the seed layer 111 may also be formed by sputter-depositing, for example, copper.
FIG. 1c schematically shows the semiconductor structure 100 with copper 113 filled into the via 109 to provide the electrical connection to the underlying metal line 104. Typically, the copper 113 is deposited by electroplating, wherein the barrier layer 110 and the copper seed layer 111 (see FIG. 1b) act as a current distribution layer connecting the substrate 101 with an external plating electrode. After depositing copper in an amount that is sufficient to reliably fill the via 109, the semiconductor structure 100 may be annealed to improve the crystallinity of the copper 113. Thereafter, the excess copper 113 may be removed by chemical mechanical polishing (CMP), wherein, at the same time, the barrier layer 110 and the copper seed layer 111 outside the via 109 are also removed and the surface 112 of the insulating layer 105 is planarized.
It turns out, however, that voids 114 may be frequently observed in the via 109, in particular, in the vicinity of the bottom of the via 109 and the bottom portion of sidewalls 115. As these voids 114 not only compromise the mechanical stability of the copper plug 113 but also significantly reduce the electrical characteristics of the copper plug 113, the reliability of the completed semiconductor structure 100 is significantly reduced, as already the failure of a single electrical connection may result in a failure of the entire integrated circuit.
In view of the above-described problems, it is, therefore, highly desirable to establish a process sequence that allows reduction of or even completely avoids the formation of voids at the bottom region of conductive vias.